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Static Timing Analysis Roadmap


In the VLSI roadmap, the writer has introduced you to the field of VLSI. This roadmap will specifically be focused on a sub domain of VLSI called as Static Timing Analysis. Before I get going into the details, I’ll give a little brief about the various sub domains within VLSI.

VLSI contains two major sub sections.

  1. Analog Circuit Design

  2. Digital Design

There is EDA (Electronic Design Automation) as well. But it is mostly Computer Science driven. Both of these sections (Analog & Digital) have Front End and the Back End Design Cycles.

I’ll briefly describe about what Front End and Back End design cycles are:


Front End Design → The Design cycle starts with the description of the problem/specification of the circuit.

Some specifications samples include:

  1. What are the inputs? Input Voltage and current ranges.

  2. What is the frequency at which the design is required to operate?

  3. What is the tech node to be used in the design?

  4. What are the P,V,T corners to be used for analysing the circuit?

  5. What are the libraries to be used? This is generally provided by the Foundry as a PDK (Process Development Kit) package.

  6. What are the design constraints? (This is developed according to the requirements of the Client by the Design Team) and so on & so forth.

So, what does a Front End Guy do?

He analyses the constraints and the specifications and develops the circuits to meet the requirements. (This is applicable for both Analog and Digital Designs). However, people perceive Front End in different ways.

In Analog design, Circuit Designer is the Front End Guy. He generally designs PLLs, Amplifiers, SRAM Memories etc. Analog circuits are designed using a S/W tool named "Cadence Virtuoso". In Digital design, RTL (Register Transfer Level) Designer is the Front End Guy. He designs subsystems like Buses, ALUs, DSP units, Camera Blocks, GPU blocks etc.

VLSI Front End Design Tools:

Designs are developed by using a H/W Description Language called Verilog & VHDL. The S/W tool used is Cadence NC Sim (Industry Std Tool). Students in the Universities can use Xilinx Vivado Tool for practising.

NOTE → Analog Designs are small (consists of a few transistors but extremely complex). Digital Designs are extremely large and are relatively less complex when compared to Analog Designs. Both Digital and Analog designs are developed keeping in mind the constraints and the design requirements.

Back End Design → Now that the circuits and the sub-systems have been designed in accordance with the design requirements, the Back End guy implements them. He implements them keeping in mind the design constraints such as Area, Frequency etc.

The Back End Implementation Engineer is responsible for the following:

  1. Where should the circuit/cell be placed in my chip?

  2. Where should the pins be placed?

  3. How should the Floorplan of the chip look like?

  4. What should be the dimension of the block/SoC ?

  5. What are the Routing Layers to be used in the design?

  6. What should be the Power Delivery Network be like?

  7. What should be Clock Planning Strategy Look like?

  8. How to meet the timing requirements of the block?

  9. Is the design DRC clean?

  10. Congestion Removal Strategies. So on and so forth.

In Analog design, the Layout Engineer is the Back End Guy. He is given with the circuit design and he plans the implementation with the circuit guy. In Digital design, the Physical Design Engineer is the Back End Guy. He is provided with subsystem synthesized RTL.

NOTE → Synthesized RTL is different from bare metal RTL. Once the RTL is developed it is synthesized (i.e the code is binded with the standard cells from the LEFs).  Synthesis is the hardware equivalent of compiling in software.

There are various sub positions under Physical Design. They are →

  1. Power Delivery Network Engineer

  2. Physical Design Engineer. (FloorPlan, Place, CTS, Route)

  3. Physical Verification Engineer.

  4. Timing Engineer

The PD Engineer does the Floor Planning of the chip, places the cells, plans the Clock Tree strategies and Routes the Design. All these are performed by using TCL scripts which is fed to the Design Shell.

VLSI Back End Design Tools:

There are two major S/W tools used for this process.

  1. Innovus by Cadence.

  2. ICC2 by Synopsys.

Now where does Timing Engineer have a role in the Design cycle?

The answer is “Everywhere”. Timing has to be met in the design stage as well as in the implementation stage. STA is one of the ways to enter the VLSI Design Industry.


The Roadmap for Static Timing Analysis is as follows:

PREREQUISITE → You must know the functioning of FLIP FLOPS (specifically D flops). If you don’t, you can learn it from the following links:

  1. Introduction to JK Flip Flop

  2. Introduction to D flip flop

  3. Truth Table, Characteristic Table and Excitation Table for D Flip Flop

  4. What is a clock?

These videos will give you a detailed insight about the basic functioning of flip flops.

Now that you know the operation of a flip flop, you need to push further to expand your “knowledge base” to sequential circuits. In fact it would be the best to go through all of their videos. You can find that here:

  1. Analysis of Clocked Sequential Circuits (with D Flip Flop)

  2. Shift Register (SISO Mode)

Assuming that you’ve gone through those tutorials, the next step is to understand what Setup and Hold Time of a flop is. You can find those here:

  1. How to do STA Introduction To Slack And Hold Timing Analysis??

  2. Introduction to data and latch timing

These videos just deliver the basic fundae. However, I would recommend the candidate to purchase Kunal Ghosh’s Lecture on STA from the online learning platform Udemy.

Why am I recommending specifically this guy’s course? It’s because of the following reasons.

  1. Short and Concise

  2. “To the point” content delivery.

His course on Physical Design is also quite good. 

The blog by VLSI-Expert is the most famous blog that almost everyone aspiring for a VLSI job goes through on a regular basis. This blog not only contains info about VLSI but also contains resume/CV recommendations and job listings. So, this is a very important site.

Assuming that you’ve gone through the blogs and the courses, now it’s time to dive deep into STA.

You have to read J.Bhasker’s “Static Timing Analysis for Nanometer Designs, A Practical Approach” completely to understand the nitty gritties of STA.

TIP → Take a print out of the book and read from it. (It helps)

Now, you’re ready to take on the VLSI Industry.

The following steps are for those who want to go even further. It contains certain site listings that might be limited to universities having the S/W Tool Licenses.

So, if your university has Cadence Tools, you can enroll into the Cadence Support Site. Once you’ve enrolled, you can search through the various articles on STA. Please be informed that these articles are of the Industry standard. Hence, they would be complex since these are real design problems faced by the Engineers.


Advanced Static Timing Analysis

Very few universities in India have got Synopsys Tool since they are very expensive. Now, if your university has one, you can create an account in SolvNet. After registering yourself in SolvNet, you can go through the Synopsys PrimeTime Manual for Advanced STA. PT-Manual is a very detailed document and is vast. It contains a lot of corner cases.

That’s about it. STA is a very vast and a challenging field in VLSI. You got to spend a lot of time with it to understand it.

Job ListingsJobs in VLSI domain can be found in VLSI Expert Site

So by now you would have got an idea as to how much is expected from a candidate by the Industry. Companies like NVIDIA, Qualcomm, Broadcom, AMD etc. hire from premium institutions and even if they hire they do not take the risk of assigning a block to a fresh candidate. They train the candidate in house even after the hiring process.

So, how does a candidate who is not from a premium institute get into these companies?

The way is to work for VLSI start-ups and gain enough knowledge and build the skill set and then get into Big Firms like Intel, Samsung etc.

Some VLSI Startups in which you can have experience→

  1. Si2Chip Technologies.

  2. Mindlance Technologies..

  3. Mirafra Technologies.  

  4. InSemi Technologies.

  5. SignOff Semiconductors so on and so forth.

How to apply to these companies?

You can either contact the HR or someone who is working in that organisation. Usually, referrals work better. Build your resume properly. And also prepare well for interviews. For interview preparation for job in VLSI domain, there is a great course in Udemy : VLSI - Essential concepts and detailed interview guide. This course will be a very good start point for interview preparation for STA.


Expected Salary for STA jobs:

A student, who has followed the roadmap and has got a stronghold in STA, can expect a CTC of up to 6LPA in start-ups and up to 16 LPA CTC for Big corporates as a fresh graduate.

Tips on CV preparation for STA jobs

VLSI Expert Site  and  Internshala are very good websites to get best tips on CV preparation for STA jobs.



Sethupathi Balakrishnan

Physical Design Engineer at Qualcomm